1. Field of the Invention
The present invention relates to a data transfer circuit for use in a semiconductor device.
2. Description of the Related Art
As shown FIG. 1, a data transfer section conventionally used in a dual-port memory is arranged between a random-accessed RAM section and, for example, a serial port section. The data transfer section is comprised of a data holding section 101 and two data transfer gate sections 102 and 103. In a read transfer cycle data bits read from the RAM section in bit parallel are first transferred to data holding section 101 via gate section 102. Data holding section 101 is accessed in bit serial so that the data bits are serially output to the serial port section via gate section 103. In a write transfer cycle, serial data bits from the serial port section are written into data holding section 101 via gate section 103. Thereafter, data holding section 101 transfers the data bits in parallel to the RAM section via gate section 102.
With the circuit arrangement of FIG. 1, however, when data bits on bit-line pairs 104a through 104b are transferred to data holding section 101 via data transfer gate section 102, if a row address strobe signal RAS goes from a "L" level to a "H" level, the data bits on the bit-line pairs will generally disappear. Thus, the timing for data transfer must be set before the signal RAS goes from "L" level to "H" level. For this reason the flexibility of determination of the data transfer timing becomes small, and the data transfer circuit is thus very hard to use.
When the bit lines are made of a material of high resistivity, it takes long to transfer data on the bit lines to data holding section 101 in the read transfer cycle. During this period of time data cannot be transferred from data holding section 101 to the serial port section. It also takes long to transfer data held in data holding section 101 onto the bit lines in a write transfer cycle. Therefore, this kind of data transfer section cannot continuously transfer data from data transfer section to the serial port section and from the serial port section to data transfer section, via gate section 103.